Hierarchical Modeling for VLSI Circuit Testing is popular PDF and ePub book, written by Debashis Bhattacharya in 2012-12-06, it is a fantastic choice for those who relish reading online the Computers genre. Let's immerse ourselves in this engaging Computers book by exploring the summary and details provided below. Remember, Hierarchical Modeling for VLSI Circuit Testing can be Read Online from any device for your convenience.
Hierarchical Modeling for VLSI Circuit Testing Book PDF Summary
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
Detail Book of Hierarchical Modeling for VLSI Circuit Testing PDF
- Author : Debashis Bhattacharya
- Release : 06 December 2012
- Publisher : Springer Science & Business Media
- ISBN : 9781461315278
- Genre : Computers
- Total Page : 168 pages
- Language : English
- PDF File Size : 10,6 Mb
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