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Functional Verification of Programmable Embedded Architectures Book PDF Summary

Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect’s knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems.

Detail Book of Functional Verification of Programmable Embedded Architectures PDF

Functional Verification of Programmable Embedded Architectures
  • Author : Prabhat Mishra
  • Release : 01 July 2005
  • Publisher : Springer Science & Business Media
  • ISBN : 0387261435
  • Genre : Computers
  • Total Page : 204 pages
  • Language : English
  • PDF File Size : 16,8 Mb

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